Maintaining a stable clock signal is often one of the fundamental requirements in modern electronics due to the need for synchronous timing of switching circuits, memory devices and data transmission. Phase-locked loops (PLL's) are commonly used to generate clock signals due to their ability to generate a clean stable output from a noisy input. Further, PLL frequency multipliers are commonly used to generate a clock signal locked to a reference frequency already available. For example, generation of a 61.440 kHz clock signal locked to a 60 Hz power line already present in the circuitry can be obtained by using a PLL frequency multiplier with a 1024 divider (61,440 Hz=60 Hz.times.1024).
Many circuits, for example telecommunications networks, must be able to switch from one clock source to another. This can occur when the first clock source is deteriorating or is going away, or when another clock source is desired for some reason. Unfortunately, switching from one clock source to another typically can cause numerous faults in the circuit being clocked if the switch is not smooth enough to be essentially `seamless` or transparent to the clocked circuit. Further, when using a phase-locked loop frequency multiplier to generate a clock signal, merely switching inputs to the PLL frequency multiplier typically can cause large variations in the output clock signal. These variations are due to the phase detector in the PLL frequency multiplier seeing large phase differences between its two inputs (one the new clock signal, the other the feedback signal from the divider). This results in a new voltage signal being sent to the voltage controlled oscillator, which causes the oscillator to output a clock signal at variance with the old clock signal. These varying clock signals typically continue until the PLL frequency multiplier has stabilized to the new input clock signal. In the meantime, the circuitry relying on the clock signal from the PLL may have incurred timing faults due to the varying clock signals output to it.
The problem thus faced is how to switch from one clock signal to another clock signal input to a PLL frequency multiplier without causing large variations in the output clock signal fed to the circuitry relying on the clock signals. One prior approach is to clamp down on or limit how much the voltage range to the voltage controlled oscillator can vary. Although this does temper variations in the output clock signal, this is really only a partial solution because this still does not prevent the clocked circuitry from incurring errors. This is because the output clock signal can still vary to an unwanted degree.
Another prior approach to maintaining a stable output clock signal when switching from one clock source to another clock source input to a PLL frequency multiplier is to increase the dampening factor of the low pass filter while making the switch, thus preventing short swings in the phase detector output from being passed on to the voltage controlled oscillator. Unfortunately, this is a cumbersome solution because it is too dependent upon matching the device characteristics of the particular low pass filter used in a given PLL frequency multiplier.
Still another prior approach is to wait out the two clock signals. Since two signals, if there is at least a slight variation in their relative frequencies, will eventually both be either high or low at the same time, a switch could be made in that instant. The problem with this solution is that one could wait a very long time for the two signals to match which is not very feasible in a working environment and is thus also an inadequate solution.